1. Field of the Invention
The present invention relates to an integrated circuit, a fabricating method for the integrated circuit and an evaluating method for the integrate circuit, more particularly, to an integrated circuit including an IC (integrated circuit) chip using a semi-insulating substrate and a ceramic substrate on which the IC chip is put and the integrated circuit which can be evaluated as to a bonding condition between the IC chip and the substrate, and to a fabricating method and an evaluating method thereof.
2. Description of the Related Art
As known, when an integrated circuit is fabricated, a processing step called die bonding is performed. The die bonding is a step where a chip (also called a die) divided in a dicing step is fixed to a substrate. It is known that there are three bonding methods such as paste bonding, solder bonding and eutectic bonding.
In an integrated circuit fabricated by mounting an IC chip using a semi-insulator such as GaAs or InP on a ceramic substrate, there are many cases where solder bonding and eutectic bonding are used for bonding the IC chip and the ceramic substrate. In solder bonding, a foil of low melting point alloy (namely, solder) is put between the chip and the substrate. Then, the foil is reflowed by heating, whereby the chip and the ceramic substrate are bonded. Additionally, in solder bonding, for example, when the wettability of the solder is not good for the chip materials or a ceramic substrate, films including materials of which the wettabilities are good are previously formed on one or both of the bonding surfaces of the chip and the ceramic substrate by a vacuum evaporation method or the like.
In eutectic bonding, the chip and the ceramic substrate are bonded by using a diffusion reaction between two elements which form a eutectic alloy. That is, in eutectic bonding, as shown in FIGS. 9(A) and 9(B), a bonding surface of a chip 31 is provided with a film 32 including one of the two elements to be the eutectic alloy and a bonding surface of a ceramic substrate 34 provided with a film 33 including the other of the two elements are brought into contact (see FIG. 9(A)) and heated temporarily, so that the chip 31 and the ceramic substrate 34 are bonded by a eutectic alloy 35 (and the film 33) (see FIG. 9(B)). In FIGS. 9(A) and 9(B), all of the film 32 is changed into a eutectic alloy, however, there is a chance that at least a portion of the film 32 remains.
In solder bonding or eutectic bonding, a bonding portion with very small thermal resistance can be formed. In eutectic bonding, however, as shown in FIG. 10, there is a chance that the eutectic alloy layer 35 is not evenly formed, so that a defect such as a cavity 50 is formed between the chip 31 and the ceramic substrate 34. In the solder bonding, there is also a that a cavity 50 is formed in a bonding portion.
In an integrated circuit like that shown in FIG. 10, a thermal resistance between the chip 31 and the ceramic substrate 34 (particularly, around the cavity 50) is high. Therefore, when this integrated circuit operates, the temperature of the chip 31 raises compared with an integrated circuit in which a bonding portion in normally formed as shown in FIG. 9(B).
Particularly, in an IC chip using a semi-insulating or insulating substrate such as GaAs (gallium arsenide), InP (indium phosphoide) and sapphire, the thermal conductivity of the substrate is low. Therefore, when the chip is not normally bonded to the ceramic substrate, the circuit fabricated on the chip does not operate normally because of the increased temperature.
Thus, it is desirable to identify integrated circuits which are not normally bonded. In conventional integrated circuits, a bonding condition is evaluated only by measuring the force required to peel the chip from the ceramic substrate or measuring the actual thermal resistance. The former is a destructive inspection, and therefore bonding conditions of the integrated circuits can not be evaluated individually by the former method. The latter is a non-destructive inspection, and can be used for integrated circuits individually, but, it takes a long time to measure the thermal resistance. Thus, in the latter method, there is no choice except for that some of a plurality of integrated circuits are evaluated as samples.